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Support system for administration and control of FSO transceiver
Janík, Lukáš ; Němeček, Jiří (referee) ; Wilfert, Otakar (advisor)
Tato práce se zabývá problematikou optických bezkabelových spojů (FSO). V úvodní kapitole jsou diskutovány přednosti, základní principy a dílčí komponenty FSO spojů. Druhá kapitola se zabývá atmosférou z pohledu šířícího se optického svazku, jejím složením, základními veličinami a jevy v ní nastávajícími. V následující kapitole je popsáno několik metod ke zmírnění jevů majících negativní vliv na kvalitu spoje. Druhá část práce se zabývá návrhem podpůrného systému pro FSO, založeném na softcore mikroprocesoru MicroBlaze, návrhem jednoduchého síťového přepínače a síťového rozhraní. Závěr práce pojednává o implementaci webového serveru a tvorbě webové prezentace umožňující vzdálenou správu FSO a jeho komponent.
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Coevolutionary Algorithm in FPGA
Hrbáček, Radek ; Vašíček, Zdeněk (referee) ; Drahošová, Michaela (advisor)
This thesis deals with the design of a hardware acceleration unit for digital image filter design using coevolutionary algorithms. The first part introduces reconfigurable logic device technology that the acceleration unit is based on. The theoretical part also briefly characterizes evolutionary and coevolutionary algorithms, their principles and applications. Traditional image filter designs are compared with the biologically inspired design methods. The hardware unit presented in this thesis exploits dual MicroBlaze system extended by custom peripherals to accelerate cartesian genetic programming. The coevolutionary image filter design is accelerated up to 58 times. The hardware platform functionality in the task of impulse noise filter design and edge detector design has been empirically analyzed.
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Implementation of the Network Traffic Filter by Microblaze in FPGA
Viktorin, Jan ; Korček, Pavol (referee) ; Kaštil, Jan (advisor)
The thesis explores the area of hardware acceleration of a software network traffic filter running inside processor MicroBlaze in the FPGA Spartan-3E. The accelerated application is widely used firewall from the Linux Kernel called iptables, more precisely its extension L7-filter. L7-filter performs lookups inside network traffic using regular expressions. Because of its significant influence on the application performance, it has been exchanged with a hardware unit controlled from the Linux Kernel. The performance has been increased more than twice.
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Compiler for EdkDSP Platform
Baručák, Robert ; Dolíhal, Luděk (referee) ; Masařík, Karel (advisor)
Goal of this bachelor's thesis was to create a compiler system for EdkDSP platform. Two different approaches to construction of compiler system for multiprocessor platform are presented. Compiler is based on LLVM compiler infrastructure. As a result, two versions of compiler system utilising hardware capabilities of EdkDSP were created. Developed solutions have a few constraints which are discussed in this paper.
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MicroBlaze processor implementation using CodAL language
Hájek, Radek ; Zachariášová, Marcela (referee) ; Pristach, Marián (advisor)
The diploma thesis contains theoretical basis, classification and function of processors. It summarizes the principle of pipelined instruction processing and the types of hazards in the microarchitecture of the processor. It also introduces design of processors using CodAL language developed by Codasip company. In the practical part of the thesis the model of MicroBlaze core developed by Xilinx company was described in the CodAL language. Designed model was tested and implemented into the FPGA device as practical example.
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High speed acquisition system
Svoboda, Tomáš ; Kováč, Michal (referee) ; Kubíček, Michal (advisor)
This master's thesis is focused on the design of a highspeed aquizition system which is based on FPGA and a highspeed AD converter with modern JESD204B interface. Considering the requirements, such as high samplig rate, the current range of available devices is limited. Therefore the market overview of the modern IC and modules was made. The resulting design is based on available modules, so the rached sampling rate is up to 5 GSa/s with 12bits resolution. Data from measurement are send to PC via Ethernet which uses lwIp stack and TEMAC core on Microblaze proccessor.
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Logic analyzer implementation into the FPGA
Kořínek, Milan ; Valach, Soběslav (referee) ; Gogol, František (advisor)
The thesis deals with the implementation of a simple logic analyzer built on the Spartan-3E Starter Kit development kit. A measuring electronics board with sixteen measuring channels and five outputs was developed. Outputs can be used as square wave generators. Inputs and outputs are protected by overvoltage protection circuitry. The application is run on a MicroBlaze software processor. The LCD touchscreen displays an easy graphical interface which can be conveniently controlled through the touch panel.
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Remote control of FPGA-based embedded system
Král, Jan ; Stejskal, Vojtěch (referee) ; Kubíček, Michal (advisor)
The bachelor’s project looks into the development of a part of Digitizer embedded system. The design is focused on the usage of FPGA-based processor managing the remote control operations and on the achievement of the sufficient bitrate for transmitting data to the ethernet network. The project summarizes used solutions and evaluates their applicability in the developed system. Matching concepts of solved problems are designed properly; in most cases they associate positive properties of used solutions. The implementations of MicroBlaze processor system and chosen modules were performed into the target device and the desired characteristics were measured with successful outcome.
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Asymmetric-Key Cryptography in Embedded Systems
Záhorský, Matej ; Kula, Michal (referee) ; Nosko, Svetozár (advisor)
Účelom tejto práce je prieskum a implementácia existujúceho asymetrického kryptografického algoritmu v FPGA a vyhodnotenie jeho výkonu. Prvá kapitola sa zameriava na vstavané systémy a FPGA, pričom popisuje ich štruktúru a použitie. V druhej kapitole je porovnanie kryptografických algoritmov a ich vlastností, ktoré umožňujú ich použitie vo vstavaných systémoch. Fázy návrhu a implementácie v tomto projekte popisujú a implementujú riešenie, ktoré zahŕňa výber a integráciu podpisovacieho algorithmu v FPGA. Dodatočné optimalizácie na zvýšenie výkonu sú taktiež naimplementované vo forme hardvérovej akcelerácie, ktoré sú zároveň porovnané s pôvodným algoritmom v kapitole vyhodnotenia.
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Network Interface for Microblaze
Janík, Lukáš
This article deals with interfacing of Xilinx MicroBlaze (UB) softcore microprocessor to 1 Gb/s Ethernet data bus via custom simple Ethernet switch. This interface is implemented on an FPGA board and serves as the lower communication layer for administration of gigabit Ethernet-tooptical bridge.
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